It is often desired to compute the parity of a multi-bit word. Many common error detection and error correction schemes such as a Hamming error correction code (ECC) require a parity computation. Parity is typically computed electrically by means of an exclusive-OR (XOR) gate. Parity computations could be performed with an n-input XOR gate (n being an integer greater than two) but in general such computations are implemented using a collection of two-input XOR gates with appropriate interconnections. However, two-input XOR gates are notoriously slow. The core of the XOR gate usually requires both the input signals and their logical complement. This complement must either be computed internally or provided externally. In case of internal computation, the gates often require two delay (computation) stages. In case of external computation, the XOR gate may require only a single delay stage, but the external circuit must suffer a delay stage penalty to provide the signal complement. There are some variations of XOR gates that do not require complement signals and require only a single delay stage of computation. However, these gates do not actively drive or buffer their output for at least some input combinations (i.e. the output is directly connected to the input). These type of gates are not suitable to be cascaded in large numbers to make n-input XOR gates because the signal drive capability gets progressively weaker as the input signals pass through multiple 2-input XOR gates.
Accordingly, there is a need in the art for improved XOR calculation architectures.